English to French Tech/Engineering Electronics / Elect Eng phase frequency detector module, quantization noise, input clock (in a patent)

-traditional Integer-N PLL (phase-locked loop), if finer output frequency resolution is desired, one approach is to pre-divide the input clock in order to lower the reference clock frequency.
-derive finer output frequency resolution is to use a Fractional-N PLL. With this approach, the feedback divider is typically controlled